Datasheet
DAC1405D750 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 31 January 2012 18 of 43
NXP Semiconductors
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating
4 to 2 MODULATION[2:0] R/W modulation
000 dual DAC: no modulation
001 positive upper single sideband
up-conversion
010 positive lower single sideband up-conversion
011 negative upper single sideband
up-conversion
100 negative lower single sideband
up-conversion
1 to 0 INTERPOLATION[1:0] R/W interpolation
01 reserved
10 4
11 8
Table 12. PLLCFG register (address 02h) bit description
Default settings are shown highlighted.
Bit Symbol Access Value Description
PLL ON PLL OFF
7 PLL_PD R/W PLL
0 switched on
1 switched off
6 - - reserved
5 PLL_DIV_PD R/W PLL divider undefined
0 switched on X
1 switched off X
4 to 3 PLL_DIV[1:0] R/W PLL divider factor Digital clock delay
00 2 130 ps
01 4 280 ps
10 8 430 ps
11 X 580 ps
2 to 1 DAC_CLK_DELAY[1:0] R/W phase shift (f
s
) undefined
00 0 X
01 120 X
10 240 X
0 DAC_CLK_POL R/W clock edge of DAC (f
s
) undefined
0 normal X
1 inverted X
Table 13. FREQNCO_LSB register (address 03h) bit description
Bit Symbol Access Value Description
7 to 0 FREQ_NCO[7:0] R/W - lower 8 bits for the NCO frequency setting
Table 11. TXCFG register (address 01h) bit description …continued
Default settings are shown highlighted.
Bit Symbol Access Value Description