Datasheet

Product data sheet Rev. 5 — 31 January 2012 17 of 43

NXP Semiconductors

DAC1405D750

Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating

10.2.4 Detailed register descriptions

Please refer to Table 9 for the register overview and relevant default values. In the

following tables, all the values shown in bold are the default values.

Table 10. COMMon register (address 00h) bit description

Default settings are shown highlighted.

Bit Symbol Access Value Description

7 3W_SPI R/W serial interface bus type

0 4 wire SPI

1 3 wire SPI

6 SPI_RST R/W serial interface reset

0no reset

1 performs a reset on all registers except 00h

5 CLK_SEL R/W data input latch

0 at CLK rising edge

1 at CLK falling edge

4 - - - reserved

3 MODE_SEL R/W input data mode

0 dual port

1 interleaved

2 CODING R/W coding

0binary

1 two’s compliment

1 IC_PD R/W power-down

0disabled

1 all circuits (digital and analog, except SPI)

are switched off

0 GAP_PD R/W internal bandgap power-down

0 power-down disabled

1 internal bandgap references are switched off

Table 11. TXCFG register (address 01h) bit description

Default settings are shown highlighted.

Bit Symbol Access Value Description

7 NCO_ON R/W NCO

0 disabled (the NCO phase is reset to 0)

1 enabled

6 NCO_LP_SEL R/W low-power NCO

0 disabled

1 NCO frequency and phase given by the five

MSBs of the registers 06h and 08h

respectively

5 INV_SIN_SEL R/W x / (sin x) function

0 disabled

1 enabled