Datasheet

DAC1405D750 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 31 January 2012 15 of 43
NXP Semiconductors
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating
The SPI timing characteristics are given in Table 8.
10.2.3 Detailed descriptions of registers
An overview of the details for all registers is provided in Table 9.
Table 8. SPI timing characteristics
Symbol Parameter Min Typ Max Unit
f
SCLK
SCLK frequency - - 15 MHz
t
w(SCLK)
SCLK pulse width 30 - - ns
t
su(SCS_N)
SCS_N set-up time 20 - - ns
t
h(SCS_N)
SCS_N hold time 20 - - ns
t
su(SDIO)
SDIO set-up time 10 - - ns
t
h(SDIO)
SDIO hold time 5 - - ns
t
w(RESET_N)
RESET_N pulse width 30 - - ns