Datasheet

DAC1405D750 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 31 January 2012 14 of 43
NXP Semiconductors
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating
In Table 7 N1 and N0 indicate the number of bytes transferred after the instruction byte.
A0 to A4: indicate which register is being addressed. In the case of a multiple transfer, this
address concerns the first register after which the next registers follow directly in a
decreasing order according to Table 9 “
Register allocation map”.
10.2.2 SPI timing description
The interface can operate at a frequency of up to 15 MHz. The SPI timing is shown in
Figure 4
.
R/W indicates the mode access, (see Table 6)
Fig 3. SPI protocol
001aaj812
RESET_N
SCS_N
SCLK
SDIO
SDO
(optional)
R/W
N1 N0 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Table 6. Read or Write mode access description
R/W Description
0 Write mode operation
1 Read mode operation
Table 7. Number of bytes transferred
N1 N0 Number of bytes
0 0 1 byte transferred
0 1 2 bytes transferred
1 0 3 bytes transferred
1 1 4 bytes transferred
Fig 4. SPI timing diagram
001aaj813
50 %
t
w(RESET_N)
t
su(SCS_N)
t
su(SDIO)
t
h(SDIO)
t
h(SCS_N)
t
w(SCLK)
50 %
RESET_N
SCS_N
SCLK
SDIO
50 %
50 %