Datasheet

DAC1405D750 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 31 January 2012 11 of 43
NXP Semiconductors
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating
Input timing (see Figure 10)
f
data
data rate Dual-port mode input C - - 185 MHz
t
w(CLK)
CLK pulse width C 40 - 60 %
t
h(i)
input hold time C 1.6 - - ns
t
su(i)
input set-up time C 0.8 - - ns
SYNC signal
t
d
delay time f
SYNC
= f
s
/ 4 C - 0.21 - ns
f
SYNC
= f
s
/8 C - 0.3 - ns
variation C - 0.27 - ps/C
Output timing
f
s
sampling frequency C - - 750 Msps
t
s
settling time to  0.5 LSB D - 20 - ns
NCO frequency range
f
NCO
NCO frequency register values
00000000h D - 0 - MHz
FFFFFFFFh D - 740 - MHz
f
step
step frequency D - 0.172 - Hz
Low-power NCO frequency range
f
NCO
NCO frequency register values
00000000h D - 0 - MHz
F8000000h D - 716.875 - MHz
f
step
step frequency D - 23.125 - MHz
Dynamic performance
SFDR spurious-free dynamic
range
f
s
= 737.28 Msps
f
data
= 92.16 MHz; B = f
data
/2
f
o
= 4 MHz; 0 dBFS C - 77 - dBc
f
data
=184.32MHz; B=f
data
/2
f
o
=19MHz; 0dBFS I - 74 - dBc
f
o
=70MHz; 0dBFS C - 86 - dBc
SFDR
RBW
restricted bandwidth
spurious-free dynamic
range
f
o
=153.6MHz; 0dBFS; f
data
= 184.32 MHz; f
s
= 737.28 Msps
B = 20 MHz C - 86 - dBc
B=100MHz C - 80.5 - dBc
B = 20 MHz; 8-tone;
500 kHz spacing
C-76- dBc
Table 5. Characteristics
…continued
V
DDA(1V8)
=V
DDD(1V8)
= 1.8 V; V
DDA(3V3)
=V
DD(IO)(3V3)
= 3.3 V; AGND, DGND and GNDIO shorted together;
T
amb
=  40  Cto+85  C; typical values measured at T
amb
=25  C; R
L
= 50  differential; I
O(fs)
= 20 mA; PLL off unless
otherwise specified.
Symbol Parameter Conditions Test
[1]
Min Typ Max Unit