DAC1405D750 Dual 14-bit DAC, up to 750 Msps; 4x and 8x interpolating Rev. 5 — 31 January 2012 Product data sheet 1. General description The DAC1405D750 is a high-speed 14-bit dual channel Digital-to-Analog Converter (DAC) with selectable 4 or 8 interpolating filters optimized for multi-carrier wireless transmitters. Thanks to its digital on-chip modulation, the DAC1405D750 allows the complex I and Q inputs to be converted from BaseBand (BB) to IF.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 3. Applications Wireless infrastructure: LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA Communication: LMDS/MMDS, point-to-point Direct Digital Synthesis (DDS) Broadband wireless systems Digital radio links Instrumentation Automated Test Equipment (ATE) 4. Ordering information Table 1.
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DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 6. Pinning information 77 VDDA(1V8) 76 AGND 78 AGND 79 VDDA(1V8) 80 AGND 81 VDDA(1V8) 82 AGND 83 VDDA(1V8) 84 AGND 85 IOUTBN 86 IOUTBP 87 AGND 88 n.c. 89 AGND 90 IOUTAP 91 IOUTAN 92 AGND 93 VDDA(1V8) 94 AGND 95 VDDA(1V8) 96 AGND 97 VDDA(1V8) 98 AGND 99 VDDA(1V8) 100 AGND 6.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 6.2 Pin description Table 2. DAC1405D750 Product data sheet Pin description Symbol Pin Type[1] Description VDDA(3V3) 1 P analog supply voltage 3.3 V AUXAP 2 O auxiliary DAC B output current AUXAN 3 O complementary auxiliary DAC B output current AGND 4 G analog ground VDDA(1V8) 5 P analog supply voltage 1.8 V VDDA(1V8) 6 P analog supply voltage 1.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating Table 2. DAC1405D750 Product data sheet Pin description …continued Symbol Pin Type[1] Description VDDD(1V8) 40 P digital supply voltage 1.8 V Q13/SELIQ 41 I Q data input bit 13 (MSB)/select IQ in Interleaved mode Q12 42 I Q data input bit 12 DGND 43 G digital ground VDDD(1V8) 44 P digital supply voltage 1.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating Table 2. Pin description …continued Symbol Pin Type[1] Description VDDA(1V8) 81 P analog supply voltage 1.8 V AGND 82 G analog ground VDDA(1V8) 83 P analog supply voltage 1.8 V AGND 84 G analog ground IOUTBN 85 O complementary DAC B output current IOUTBP 86 O DAC B output current AGND 87 G analog ground n.c.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 7. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions VDD(IO)(3V3) input/output supply voltage (3.3 V) Min Max Unit 0.5 +4.6 V VDDA(3V3) analog supply voltage (3.3 V) 0.5 +4.6 V VDDA(1V8) analog supply voltage (1.8 V) 0.5 +3.0 V VDDD(1V8) digital supply voltage (1.8 V) 0.5 +3.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 9. Characteristics Table 5. Characteristics VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together; Tamb = 40 C to +85 C; typical values measured at Tamb = 25 C; RL = 50 differential; IO(fs) = 20 mA; PLL off unless otherwise specified. Test[1] Min Typ Max Unit input/output supply voltage (3.3 V) I 3.0 3.3 3.6 V VDDA(3V3) analog supply voltage (3.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating Table 5. Characteristics …continued VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together; Tamb = 40 C to +85 C; typical values measured at Tamb = 25 C; RL = 50 differential; IO(fs) = 20 mA; PLL off unless otherwise specified.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating Table 5. Characteristics …continued VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together; Tamb = 40 C to +85 C; typical values measured at Tamb = 25 C; RL = 50 differential; IO(fs) = 20 mA; PLL off unless otherwise specified.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating Table 5. Characteristics …continued VDDA(1V8) = VDDD(1V8) = 1.8 V; VDDA(3V3) = VDD(IO)(3V3) = 3.3 V; AGND, DGND and GNDIO shorted together; Tamb = 40 C to +85 C; typical values measured at Tamb = 25 C; RL = 50 differential; IO(fs) = 20 mA; PLL off unless otherwise specified.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 10. Application information 10.1 General description The DAC1405D750 is a dual 14-bit DAC which operates at up to 750 Msps. Each DAC consists of a segmented architecture, comprising a 6-bit thermometer sub-DAC and an 8-bit binary weighted sub-DAC.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating RESET_N SCS_N SCLK SDIO R/W N1 N0 A4 A3 A2 A1 A0 SDO (optional) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 001aaj812 R/W indicates the mode access, (see Table 6) Fig 3. SPI protocol Table 6.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating The SPI timing characteristics are given in Table 8. Table 8.
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DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 10.2.4 Detailed register descriptions Please refer to Table 9 for the register overview and relevant default values. In the following tables, all the values shown in bold are the default values. Table 10. COMMon register (address 00h) bit description Default settings are shown highlighted.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating Table 11. TXCFG register (address 01h) bit description …continued Default settings are shown highlighted.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating Table 14. FREQNCO_LISB register (address 04h) bit description Bit Symbol Access Value Description 7 to 0 FREQ_NCO[15:8] R/W Table 15. - lower intermediate 8 bits for the NCO frequency setting FREQNCO_UISB register (address 05h) bit description Bit Symbol Access Value Description 7 to 0 FREQ_NCO[23:16] R/W Table 16.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating Table 21. DAC_A_Cfg_3 register (address 0Bh) bit description Bit Symbol Access Value Description 7 to 6 DAC_A_GAIN_ COARSE[3:2] R/W - most significant 2 bits for the DAC A gain setting for coarse adjustment 5 to 0 DAC_A_ OFFSET[11:6] R/W - most significant 6 bits for the DAC A offset Table 22. DAC_B_Cfg_1 register (address 0Ch) bit description Default settings are shown highlighted.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating Table 26. SYNC_Cfg register (address 10h) bit description Default settings are shown highlighted. Bit Symbol Access Value Description 7 SYNC_DIV R/W fs divided by 6 SYNC_SEL 5 to 0 - Bit 4 1 8 R/W SYNC selection - Table 27.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 10.2.5 Recommended configuration It is recommended that the following additional settings are used to obtain optimum performance at up to 750 Msps. Table 31. Recommended configuration Address Value Dec Hex Bin Dec Hex 17 11h 00001010 10 0Ah 19 13h 01101100 108 6Ch 20 14h 01101100 108 6Ch 10.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 10.3.2 Interleaved mode The data input for the Interleaved mode operation is illustrated in Figure 6. FIR 1 LATCH I FIR 2 2× FIR 3 2× 2× I13 to I0 FIR 1 LATCH Q Q13/SELIQ FIR 2 2× FIR 3 2× 2× 001aal654 Fig 6. Interleaved mode operation In Interleaved mode, both DACs use the same data input at twice the Dual-port mode frequency. Data enters the latch on the rising edge of the internal clock signal.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 10.4 Input clock The DAC1405D750 can operate at the following clock frequencies: PLL on: up to 185 MHz in Dual-port mode and up to 370 MHz in Interleaved mode PLL off: up to 750 MHz The input clock is LVDS compliant (see Figure 8) but it can also be interfaced with CML differential sine wave signal (see Figure 9). CLKINP LVDS LVDS Zdiff = 100 Ω 100 Ω CLKINN 001aah021 Fig 8.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating tsu(i) I13 to I0/ Q13 to Q0 90 % SYNC (SYNCP − SYNCN) th(i) 90 % N N+1 N+2 50 % 001aal384 Fig 10. Input timing diagram when internal PLL bypassed (off) 10.5.1 Timing when using the internal PLL (PLL on) In Table 33 the links between internal and external clocking are defined.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating Table 36.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 10.7.1 NCO in 32-bit When using the NCO, the frequency can be set by the four registers FREQNCO_LSB, FREQNCO_LISB, FREQNCO_UISB and FREQNCO_MSB over 32 bits. The frequency for the NCO in 32-bit is calculated as follows: M fs f NCO = -------------32 2 (1) where M is the decimal representation of FREQ_NCO[31:0]. The phase of the NCO can be set from 0 to 360 by both registers PHINCO_LSB and PHINCO_MSB over 16 bits.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 10.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating VDDA(1V8) REF. BANDGAP 100 kΩ 100 nF AGND AGND 953 Ω (1 %) GAPOUT VIRES DAC CURRENT SOURCES ARRAY aaa-002266 Fig 11. Internal reference configuration This configuration is optimum for temperature drift compensation because the bandgap reference voltage can be matched to the voltage across the feedback resistor.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating Table 39. IO(fs) coarse adjustment …continued Default settings are shown highlighted. DAC_GAIN_COARSE[3:0] IO(fs) (mA) Decimal Binary 12 1100 18.5 13 1101 20.0 14 1110 21.0 15 1111 22.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating Table 41. Digital offset adjustment Default settings are shown highlighted. DAC_OFFSET[11:0] Offset applied Decimal Two’s complement 2048 1000 0000 0000 4096 2047 1000 0000 0001 4094 ... ... ... 1 1111 1111 1111 2 0 0000 0000 0000 0 +1 0000 0000 0001 +2 ... ... ... +2046 0111 1111 1110 +4092 +2047 0111 1111 1111 +4094 10.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 10.13 Auxiliary DACs The DAC1405D750 integrates 2 auxiliary DACs that can be used to compensate for any offset between the DAC and the next stage in the transmission path. Both auxiliary DACs have a resolution of 10-bit and are current sources (referenced to ground).
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating The DAC1405D750 differential outputs can operate up to 2 Vo(p-p). In this configuration, it is recommended to connect the center tap of the transformer to a 62 resistor connected to the 3.3 V analog power supply, in order to adjust the DC common-mode to approximately 2.7 V (see Figure 14).
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating Figure 16 provides an example of a connection to an AQM with a 3.3 VI(cm) common-mode input level. VDDA(3V3) (1) 54.9 Ω 5V 54.9 Ω 750 Ω AQM (Vi(cm) = 3.3 V) (2) 750 Ω 237 Ω IOUTnP BBP 237 Ω IOUTnN BBN 1.27 kΩ 1.27 kΩ (1) IOUTnP/IOUTnN; V o(cm) = 2.75 V; Vo(dif)(p-p) = 1.97 V (2) BBP/BBN; V i(cm) = 3.3 V; Vi(dif)(p-p) = 1.5 V 001aaj542 Fig 16. An example of a DC interface to a 3.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating Figure 18 provides an example of a DC interface with the auxiliary DACs to an AQM with a 3.3 VI(cm) common-mode input level. 3.3 V 54.9 Ω (1) AQM (Vi(cm) = 3.3 V) 5V 54.9 Ω 750 Ω 750 Ω (2) 237 Ω IOUTnP BBP 237 Ω IOUTnN BBN 634 Ω 634 Ω 442 Ω 442 Ω AUXnP AUXnN (1) IOUTnP/IOUTnN; V o(cm) = 2.75 V; Vo(dif)(p-p) = 1.96 V (2) BBP/BBN; V i(cm) = 3.3 V; Vi(dif)(p-p) = 1.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating VDDA(3V3) 66.5 Ω (1) 5V 66.5 Ω 2 kΩ AQM (Vi(cm) = 0.5 V) (2) 2 kΩ 10 nF IOUTnP BBP 10 nF IOUTnN BBN 0 mA to 20 mA 174 Ω 174 Ω 34 Ω 34 Ω AUXnP AUXnN 1.1 mA (typ.) (1) IOUTnP/IOUTnN; V o(cm) = 2.65 V; Vo(dif)(p-p) = 1.96 V (2) BBP/BBN; V i(cm) = 0.5 V; Vi(dif)(p-p) = 1.96 V; offset correction up to 70 mV 001aaj589 Fig 19. An example of an AC interface to a 0.5 VI(cm) AQM using auxiliary DACs 10.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 11. Package outline HTQFP100: plastic thermal enhanced thin quad flat package; 100 leads; body 14 x 14 x 1 mm; exposed die pad SOT638-1 c y exposed die pad side X Dh A 75 51 76 50 ZE e E HE Eh A A2 (A3) A1 w M θ bp Lp pin 1 index L detail X 26 100 1 25 bp e w M ZD v M A D B HD v M B 0 10 mm scale DIMENSIONS (mm are the original dimensions) A UNIT max. mm 1.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 12. Abbreviations Table 43.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 13. Glossary Spurious-Free Dynamic Range (SFDR): — The ratio between the RMS value of the reconstructed output sine wave and the RMS value of the largest spurious observed (harmonic and non-harmonic, excluding DC component) in the frequency domain.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 14. Revision history Table 44. Revision history Document ID Release date Data sheet status Change notice Supersedes DAC1405D750 v.5 20120131 Product data sheet - DAC1405D750 v.4 Modifications: • • • • Section 2 “Features and benefits” has been updated. The values for VO(ref) in Table 5 “Characteristics” have been updated. Section 10.2.1 “Protocol description” has been updated. Section 10.10.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
DAC1405D750 NXP Semiconductors Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . .