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ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 4 — 17 December 2010 30 of 42
NXP Semiconductors
ADC1415S series
Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs
Fig 29. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR
Fig 30. Default mode at start-up: SCLK HIGH = two’s complement; SDIO LOW = CMOS
CS
SDIO
(CMOS LVDS DDR)
SCLK
(Data format)
Offset binary, LVDS DDR
default mode at start-up
005aaa06
3
SDIO
(CMOS LVDS DDR)
SCLK
(Data format)
two's complement, CMOS
default mode at start-up
005aaa06
4
CS