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ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 4 — 17 December 2010 3 of 42
NXP Semiconductors
ADC1415S series
Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs
5. Block diagram
Fig 1. Block diagram
ADC1415S
SPI
OUTPUT
DRIVERS
OUTPUT
DRIVERS
SYSTEM
REFERENCE AND
POWER
MANAGEMENT
ERROR
CORRECTION AND
DIGITAL
PROCESSING
ADC CORE
14-BIT
PIPELINED
S/H
INPUT
STAGE
INP
OTR
SDIO/ODS
SCLK/DFS
PWD
REFT
CMOS:
D13 to D0
or
LVDS DDR:
D12_D13_P
to D0_D1_P
D12_D13_M
to D0_D1_M
INM
CLOCK INPUT
STAGE AND DUTY
CYCLE CONTROL
REFB
CLKM
CLKP
SENSE
VREF
VCM
005aaa10
1
CS
OE
INPUT
BUFFER
CMOS:
DAV
or
LVDS DDR:
DAVP
DAVM