Information

ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 4 — 17 December 2010 26 of 42
NXP Semiconductors
ADC1415S series
Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs
11.5.2 Digital output buffers: LVDS DDR mode
The digital output buffers can be configured as LVDS DDR by setting bit LVDS_CMOS to
logic_1 (see Table 23
).
Each output should be terminated externally with a 100 Ω resistor (typical) at the receiver
side (Figure 26
) or internally via SPI control bits LVDS_INT_TER[2:0] (see Figure 27 and
Table 32
).
The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via
the SPI (bits DAVI[1:0] and DATAI[1:0]; see Table 31
) in order to adjust the output logic
voltage levels.
Fig 26. LVDS DDR digital output buffer - externally terminated
Fig 27. LVDS DDR digital output buffer - internally terminated
Table 13. LVDS DDR output register 2
LVDS_INT_TER[2:0] Resistor value (Ω)
000 no internal termination
001 300
010 180
011 110
100 150
VCCO
3.5 mA
typ
D
n
P/D
n + 1
P
D
n
M/D
n + 1
M
OGND
100 Ω
−
005aaa05
8
+
−
+
RECEIVER
VCCO
OGND
005aaa05
9
D
x
P/D
x + 1
P
D
x
M/D
x + 1
M
100 Ω
3.5 mA
typ
+
−
+
−
RECEIVER