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ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 4 — 17 December 2010 22 of 42
NXP Semiconductors
ADC1415S series
Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs
Figure 18 to Figure 21 illustrate how to connect the SENSE and VREF pins to select the
required reference voltage source.
11.3.2 Programmable full-scale
The full-scale is programmable between 1 V (peak-to-peak) to 2 V (peak-to-peak)
(see Table 12
).
11.3.3 Common-mode output voltage (V
O(cm)
)
A 0.1 μF filter capacitor should be connected between pin VCM and ground.
11.3.4 Biasing
The common-mode input voltage (V
I(cm)
) on pins INP and INM is set internally. The input
buffer bias current can be set to one of three levels (high, medium or low) via the SPI (see
Table 22
).
Fig 18. Internal reference, 2 V (p-p) full scale Fig 19. Internal reference, 1 V (p-p) full scale
Fig 20. External reference, 1 V (p-p) to 2 V (p-p)
full-scale
Fig 21. Internal reference via SPI, 1 V (p-p) to 2 V (p-p)
full-scale
330 pF
VREF
SENSE
005aaa11
6
REFERENCE
EQUIVALENT
SCHEMATIC
330
pF
005aaa11
7
VREF
SENSE
REFERENCE
EQUIVALENT
SCHEMATIC
0.1 μF
VDDA
V
005aaa11
9
VREF
SENSE
REFERENCE
EQUIVALENT
SCHEMATIC
REFERENCE
EQUIVALENT
SCHEMATIC
330 pF
005aaa11
8
VREF
SENSE
Table 12. Reference SPI Gain Control
INTREF Gain Full-scale (p-p)
000 0 dB 2 V
001 −1dB 1.78V
010 −2dB 1.59V
011 −3dB 1.42V
100 −4dB 1.26V
101 −5dB 1.12V
110 −6dB 1V
111 reserved x