Information

ADC1415S_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 4 — 17 December 2010 19 of 42
NXP Semiconductors
ADC1415S series
Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs
The integrated input buffer offers the following advantages:
• The kickback effect is avoided - the charge injection and glitches generated by the
S/H input stage are isolated from the input circuitry. So there’s no need for additional
filtering.
• The input capacitance is very low and constant over a wide frequency range, which
makes the ADC1415S easy to drive.
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
Fig 14. Input sampling circuit and input buffer
005aaa107
INP
package ESD parasitics
switch
R
on
= 15 Ω
4 pF
4 pF
sampling
capacitor
sampling
capacitor
switch
R
on
= 15 Ω
INM
8
7
internal
clock
internal
clock
INPUT
BUFFER