Datasheet

ADC1213D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 9 June 2011 7 of 42
NXP Semiconductors
ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
P power dissipation Power-down mode - 30 - mW
Standby mode - 200 - mW
Clock inputs: pins CLKP and CLKM (AC-coupled)
Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
V
i(clk)dif
differential clock input
voltage
peak-to-peak - 0.8 - V
SINE
V
i(clk)dif
differential clock input
voltage
peak-to-peak 0.8 1.5 - V
Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS)
V
IL
LOW-level input voltage - - 0.3V
DDA
V
V
IH
HIGH-level input voltage 0.7V
DDA
-- V
Logic inputs: Power-down: pins CFG0 to CFG3, SCRAMBLER, SWING_0, SWING_1, and RESET
V
IL
LOW-level input voltage - 0 - V
V
IH
HIGH-level input voltage - 0.66V
DDD
-V
I
IL
LOW-level input current 6- +6 A
I
IH
HIGH-level input current 30 - +30 A
SPI: pins CS
, SDIO, and SCLK
V
IL
LOW-level input voltage 0 - 0.3V
DDA
V
V
IH
HIGH-level input voltage 0.7V
DDA
-V
DDA
V
I
IL
LOW-level input current 10 - +10 A
I
IH
HIGH-level input current 50 - +50 A
C
I
input capacitance - 4 - pF
Analog inputs: pins INAP, INAM, INBP, and INBM
I
I
input current track mode 5- +5 A
R
I
input resistance track mode - 15 - 
C
I
input capacitance track mode - 5 - pF
V
I(cm)
common-mode input
voltage
track mode 0.9 1.5 2 V
B
i
input bandwidth - 600 - MHz
V
I(dif)
differential input voltage peak-to-peak 1 - 2 V
Voltage controlled regulator output: pins VCMA and VCMB
V
O(cm)
common-mode output
voltage
-V
DDA
/ 2 - V
I
O(cm)
common-mode output
current
-4 - mA
Table 5. Static characteristics
[1]
…continued
Symbol Parameter Conditions Min Typ Max Unit