Datasheet

ADC1213D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 9 June 2011 3 of 42
NXP Semiconductors
ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
5. Block diagram
Fig 1. Block diagram
ERROR
CORRECTION AND
DIGITAL
PROCESSING
CLOCK INPUT
STAGE & DUTY
CYCLE CONTROL
ADC A CORE
12-BIT
PIPELINED
T/H
INPUT
STAGE
ERROR
CORRECTION AND
DIGITAL
PROCESSING
CLOCK INPUT
STAGE & DUTY
CYCLE CONTROL
SYSTEM
REFERENCE AND
POWER
MANAGEMENT
ADC B CORE
12-BIT
PIPELINED
T/H
INPUT
STAGE
ADC1213D
DLL
PLL
FRAME ASSEMBLY
SERIALIZER A
SPI
OUTPUT
BUFFER A
SERIALIZER B
OUTPUT
BUFFER B
SCRAMBLER A
ENCODER 8-bit/10-bit A
SCRAMBLER B
ENCODER 8-bit/10-bit B
8-bit 8-bit
INAP
INAM
CLKP
CLKM
INBP
SCRAMBLER RESET
INBM
8-bit8-bit 10-bit
10-bit
SWING_n
SWING_n
SYNCP
SCLK
CFG (0 to 3) SDIO
CS
SYNCN
CMLNB
CMLPB
CMLNA
CMLPA
OTR
D11 to D0
D11 to D0
OTR
005aaa120
REFAT
REFAB
REFBB
REFBT
VCMA
VREF
SENSE
VCMB