Datasheet

ADC1213D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 9 June 2011 29 of 42
NXP Semiconductors
ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
11.6.4 JESD204A digital control registers
Table 23. Register Test pattern 1 (address 0014h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 3 - - 00000 not used
2 to 0 TESTPAT_1[2:0] R/W digital test pattern:
000 off
001 mid-scale
010  FS
011 + FS
100 toggle ‘1111..1111’/’0000..0000’
101 custom test pattern, to be written in register 0015h and 0016h
110 ‘010101...’
111 ‘101010...’
Table 24. Register Test pattern 2 (address 0015h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 0 TESTPAT_2[11:4] R/W 00000000 custom digital test pattern (bit 11 to 4)
Table 25. Register Test pattern 3 (address 0016h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 TESTPAT_3[3:0] R/W 0000 custom digital test pattern (bit 3 to 0)
3 to 0 - - 0000 not used
Table 26. Ser_Status (address 0801h)
Default values are highlighted.
Bit Symbol Access Value Description
7 RXSYNC_ERROR R 0 set to 1 when a synchronization error occurs
6 to 4 RESERVED[2:0] - 010 reserved
3 to 2 - - 0 not used
1POR_TST R 1 power-on-reset
0 RESERVED - - reserved
Table 27. Ser_Reset (address 0802h)
Default values are highlighted.
Bit Symbol Access Value Description
7SW_RST R/W0 initiates a software reset of the JESD204Aunit
6 to 4 - - 000 not used
3FSM_SW_RSTR/W0 initiates a software reset of the internal state machine of
JESD204A unit
2 to 0 - - 000 not used