Datasheet
ADC1213D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 9 June 2011 28 of 42
NXP Semiconductors
ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
0 DCS_EN R/W duty cycle stabilizer enable:
0 disable
1 active
Table 20. Register Clock (address 0006h)
…continued
Default values are highlighted.
Bit Symbol Access Value Description
Table 21. Register Vref (address 0008h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 - - 0000 not used
3 INTREF_EN R/W enable internal programmable VREF mode:
0 disable
1 active
2 to 0 INTREF[2:0] R/W programmable internal reference:
000 0 dB (FS=2 V)
001 1 dB (FS=1.78 V)
010 2 dB (FS=1.59 V)
011 3 dB (FS=1.42 V)
100 4 dB (FS=1.26 V)
101 5 dB (FS=1.12 V)
110 6 dB (FS=1 V)
111 not used
Table 22. Digital offset adjustment (address 0013h)
Default values are highlighted.
Register offset:
Decimal DIG_OFFSET[5:0]
+31 011111 +31 LSB
... ... ...
0 000000 0
... ... ...
32 100000 32 LSB