Datasheet

ADC1213D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 9 June 2011 22 of 42
NXP Semiconductors
ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
11.5.2 ADC core output codes versus input voltage
Table 13 shows the data output codes for a given analog input voltage.
Fig 22. Detailed view of the JESD204A serializer with debug functionality
N
AND
CS
N
AND
CS
00
SCR
SCR
PRBS
8-bit/
10-bit
01
00
01
00
01
10
11
8-bit/
10-bit
PRBS
'0'
'0/1'
PRBS
'0'
'0/1'
PRBS
8
8
N + CS
N + CS
12 + 112 + 1
12 + 1
ADC A
PLL
AND
DLL
frame CLK
character CLK
bit CLK
10
10
11
10
01
00
SER
SER
11
10
00
11
10
00
× 1
× F
× 10F
DUMMY
ADC_PD
ADC_PD
ADC B
PRBS
FSM
(frame assembly
character
replication
ILA
test mode)
FRAME
ASSEMBLY
005aaa175
sync_request
12 + 1
ADC_MODE[1:0]
SCR_IN_MODE[1:0]
SCR_IN_MODE[1:0]
LANE_MODE[1:0]
SWING_SEL[2:0]
LANE_POL
LANE_MODE[1:0]
LANE_POL
12 + 1
12 + 1
DUMMY
PRBS
ADC_MODE[1:0]
Table 13. Output codes versus input voltage
INP  INM (V) Offset binary Two’s complement OTR
< 1 0000 0000 0000 1000 0000 0000 1
1.0000000 0000 0000 0000 1000 0000 0000 0
0.9995117 0000 0000 0001 1000 0000 0001 0
0.9990234 0000 0000 0010 1000 0000 0010 0
0.9985352 0000 0000 0011 1000 0000 0011 0
0.9980469 0000 0000 0100 1000 0000 0100 0
.... .... .... 0
0.0009766 0111 1111 1110 1111 1111 1110 0
0.0004883 0111 1111 1111 1111 1111 1111 0
0.0000000 1000 0000 0000 0000 0000 0000 0
+0.0004883 1000 0000 0001 0000 0000 0001 0
+0.0009766 1000 0000 0010 0000 0000 0010 0
.... .... .... 0
+0.9980469 1111 1111 1011 0111 1111 1011 0