Datasheet

ADC1213D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 9 June 2011 19 of 42
NXP Semiconductors
ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
11.3.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in Figure 18. The common-mode
voltage of the differential input stage is set via 5 k internal resistors.
a. Sine clock input b. Sine clock input (with transformer)
c. LVPECL clock input
Fig 17. Differential clock input
Sine
clock input
CLKP
CLKM
005aaa173
Sine
clock input
CLKP
CLKM
005aaa054
LVPECL
clock input
005aaa172
CLKP
CLKM
V
cm(clk)
= common-mode voltage of the differential input stage.
Fig 18. Equivalent input circuit
CLKP
CLKM
005aaa081
5 kΩ 5 kΩ
V
cm(clk)
SE_SEL SE_SEL
package ESD parasitics