Datasheet

ADC1213D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 9 June 2011 18 of 42
NXP Semiconductors
ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
11.2.4 Biasing
The common-mode output voltage, V
O(cm)
, should be set externally to 1.5 V (typical). The
common-mode input voltage, V
I(cm)
, at the inputs to the sample-and-hold stage
(pins INAM, INBM, INAP, and INBP) must be between 0.9 V and 2 V for optimal
performance.
11.3 Clock input
11.3.1 Drive modes
The ADC1213D can be driven differentially (LVPECL). It can also be driven by a
single-ended Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS) signal
connected to pin CLKP (pin CLKM should be connected to ground via a capacitor) or pin
CLKM (pin CLKP should be connected to ground via a capacitor).
Fig 15. Reference equivalent schematic
1.5 V
VCMA
VCMB
0.1 μF
PACKAGE ESD PARASITICS
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COMMON MODE
REFERENCE
ADC CORE
a. Rising edge LVCMOS b. Falling edge LVCMOS
Fig 16. LVCMOS single-ended clock input
LVCMOS
clock input
CLKP
CLKM
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LVCMOS
clock input
CLKP
CLKM