Datasheet

ADC1213D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 9 June 2011 16 of 42
NXP Semiconductors
ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
11.2 System reference and power management
11.2.1 Internal/external reference
The ADC1213D has a stable and accurate built-in internal reference voltage to adjust the
ADC full-scale. This reference voltage can be set internally via SPI or with pin VREF and
SENSE (see Figure 11
to Figure 14), in 1 dB steps between 0 dB and 6 dB, via SPI
control bits INTREF[2:0] (when bit INTREF_EN = logic 1; see Table 21
). The equivalent
reference circuit is shown in Figure 10
. An external reference is also possible by providing
a voltage on pin VREF as described in Figure 13
.
If bit INTREF_EN is set to logic 0, the reference voltage is determined either internally or
externally as detailed in Table 10
.
Fig 10. Reference equivalent schematic
Table 10. Reference modes
Mode SPI bit, “Internal
reference”
SENSE pin VREF pin Full-scale
(V (p-p))
Internal (Figure 11
) 0 GND 330 pF capacitor
to GND
2
Internal (Figure 12
) 0 VREF pin = SENSE pin and
330 pF capacitor to GND
1
External (Figure 13
)0 V
DDA
external voltage
from 0.5 V to 1 V
1 to 2
Internal, SPI mode
(Figure 14
)
1 VREF pin = SENSE pin and
330 pF capacitor to GND
1 to 2
EXT_ref
EXT_ref
001aan670
REFAT/
REFBT
REFAB/
REFBB
SENSE
VREF
SELECTION
LOGIC
BANDGAP
REFERENCE
ADC CORE
BUFFER
REFERENCE
AMP