Datasheet

ADC1213D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 9 June 2011 14 of 42
NXP Semiconductors
ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
11.1.2 Anti-kickback circuitry
Anti-kickback circuitry (RC filter in Figure 7) is needed to counteract the effects of a
charge injection generated by the sampling capacitance.
The RC filter is also used to filter noise from the signal before it reaches the sampling
stage. The value of the capacitor should be chosen to maximize noise attenuation without
degrading the settling time excessively.
The component values are determined by the input frequency and should be selected so
as not to affect the input bandwidth.
Fig 6. Input sampling circuit
005aaa069
INAP
INBP
package ESD parasitics
switch
R
on
= 15 Ω
4 pF
4 pF
C
s
C
s
switch
R
on
= 15 Ω
INAM
INBM
1, 14
2, 13
internal
clock
internal
clock
Fig 7. Anti-kickback circuit
001aan679
R
R
C
INAP/
INBP
INAM/
INBM