Datasheet
ADC1213D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 9 June 2011 13 of 42
NXP Semiconductors
ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
10.4 SPI timing
[1] Typical values measured at V
DDA
=3V, V
DDD
=1.8V, T
amb
=25C. Minimum and maximum values are
across the full temperature range T
amb
= 40 C to +85 C at V
DDA
=3V, V
DDD
= 1.8 V; V
I
(INAP,
INBP) V
I
(INAM,INBM) = 1 dBFS; internal reference mode; 100 differential applied to serial outputs;
unless otherwise specified.
11. Application information
11.1 Analog inputs
11.1.1 Input stage description
The analog input of the ADC1213D supports a differential or a single-ended input drive.
Optimal performance is achieved using differential inputs with the common-mode input
voltage (V
I(cm)
) on pins INxP and INxM set to 0.5V
DDA
.
The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
via a programmable internal reference (see Section 11.2
and Table 21).
Figure 6
shows the equivalent circuit of the sample-and-hold input stage, including
ElectroStatic Discharge (ESD) protection and circuit and package parasitics.
Table 8. SPI timing characteristics
[1]
Symbol Parameter Conditions Min Typ Max Unit
t
w(SCLK)
SCLK pulse width - 40 - ns
t
w(SCLKH)
SCLK HIGH pulse width - 16 - ns
t
w(SCLKL)
SCLK LOW pulse width - 16 - ns
t
su
set-up time data to SCLK H - 5 - ns
CS
to SCLK H - 5 - ns
t
h
hold time data to SCLK H - 2 - ns
CS
to SCLK H - 2 - ns
f
clk(max)
maximum clock frequency - 25 - MHz
Fig 5. SPI timing
t
su
SDIO
SCLK
R/W
W1
W0 A12 A11 D2 D1
D0
t
su
t
h
t
h
t
w(SCLK)
005aaa065
CS
t
w(SCLKL)
t
w(SCLKH)