Datasheet

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ADC1213D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 9 June 2011 11 of 42 NXP Semiconductors
ADC1213D series
Dual 12-bit ADC; serial JESD204A interface
[1] Typical values measured at V
DDA
=3V, V
DDD
=1.8V, T
amb
=25C. Minimum and maximum values are across the full temperature range T
amb
= 40 C to +85 C at V
DDA
=3V,
V
DDD
= 1.8 V; V
I
(INAP, INBP)  V
I
(INAM, INBM) = 1 dBFS; internal reference mode; 100  differential applied to serial outputs; unless otherwise specified.
10.2 Clock and digital output timing
[1] Typical values measured at V
DDA
=3V, V
DDD
=1.8V, T
amb
=25C. Minimum and maximum values are across the full temperature range T
amb
= 40 C to +85 C at V
DDA
=3V,
V
DDD
= 1.8 V; V
I
(INAP, INBP)  V
I
(INAM, INBM) = 1 dBFS; internal reference mode; 100 W differential applied to serial outputs; unless otherwise specified.
IMD intermodulation distortion f
i
=3MHz -89--89 --88--89-dBc
f
i
=30MHz -88--88--88--88-dBc
f
i
=70MHz -87--87--86--86-dBc
f
i
= 170 MHz - 84 - - 85 - - 83 - - 84 - dBc

ct(ch)
channel crosstalk f
i
= 70 MHz - 100 - - 100 - - 100 - - 100 - dBc
Table 6. Dynamic characteristics
[1]
…continued
Symbol Parameter Conditions ADC1213D065 ADC1213D080 ADC1213D105 ADC1213D125 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Table 7. Clock and digital output characteristics
[1]
Symbol Parameter Conditions ADC1213D065 ADC1213D080 ADC1213D105 ADC1213D125 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Clock timing input: pins CLKP and CLKM
f
clk
clock frequency 45 - 65 60 - 80 75 - 105 100 - 125 Msps
t
lat(data)
data latency time clock cycles 307 - 850 250 - 283 190 - 226 160 - 170 ns

clk
clock duty cycle DCS_EN = logic 1 30 50 70 30 50 70 30 50 70 30 50 70 %
DCS_EN = logic 0 45 50 55 45 50 55 45 50 55 45 50 55 %
t
d(s)
sampling delay time - 0.8 - - 0.8 - - 0.8 - - 0.8 - ns
t
wake
wake-up time -76- -76- -76- -76-s