Datasheet

ADC1212D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 4 March 2011 9 of 42
NXP Semiconductors
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
[1] Typical values measured at V
DDA
=3V, V
DDO
=1.8V, T
amb
=25C; minimum and maximum values are across the full temperature
range T
amb
= 40 C to +85 C at V
DDA
=3V, V
DDO
= 1.8 V; V
INAP
 V
INAM
= 1 dBFS; V
INBP
 V
INBM
= 1 dBFS; internal reference
mode; applied to CMOS and LVDS interface; unless otherwise specified.
Digital outputs, LVDS DDR mode: pins DA10_DA11_P to DA0_DA1_P, DA10_DA11_M to DA0_DA1_M,
DB10_DB11_P to DB0_DB1_P, DB10_DB11_M to DB0_DB1_M; DAVP and DAVM
Output levels, V
DDO
= 3 V only, R
L
= 100 
V
O(offset)
output offset voltage output buffer current set to
3.5 mA
-1.2-V
V
O(dif)
differential output voltage output buffer current set to
3.5 mA
-350-mV
C
O
output capacitance - 3 - pF
Analog inputs: pins INAP, INAM, INBP and INBM
I
I
input current 5- +5A
R
I
input resistance - 19.8 - k
C
I
input capacitance - 2.8 - pF
V
I(cm)
common-mode input voltage V
INAP
=V
INAM
; V
INBP
=V
INBM
0.9 1.5 2 V
B
i
input bandwidth - 600 - MHz
V
I(dif)
differential input voltage peak-to-peak 1 - 2 V
Common-mode output voltage: pins VCMA and VCMB
V
O(cm)
common-mode output voltage - 0.5V
DDA
-V
I
O(cm)
common-mode output current - 4 - mA
I/O reference voltage: pin VREF
V
VREF
voltage on pin VREF output - 0.5 to 1 - V
input 0.5 - 1 V
Accuracy
INL integral non-linearity 1.25 0.25 +5 LSB
DNL differential non-linearity guaranteed no missing codes 0.95 0.5 +0.95 LSB
E
offset
offset error - 2-mV
E
G
gain error - 0.5 - %FS
M
G(CTC)
channel-to-channel gain
matching
-1.1-%
Supply
PSRR power supply rejection ratio 200 mV (p-p) on pin VDDA;
f
i
=DC
- 37 - dB
Table 6. Static characteristics
[1]
…continued
Symbol Parameter Conditions Min Typ Max Unit