Datasheet

ADC1212D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 4 March 2011 8 of 42
NXP Semiconductors
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
P power dissipation ADC1212D125;
analog supply only
- 1230 - mW
ADC1212D105;
analog supply only
-1120-mW
ADC1212D080;
analog supply only
-855-mW
ADC1212D065;
analog supply only
-780-mW
Power-down mode - 24 - mW
Sleep mode - 80 - mW
Clock inputs: pins CLKP and CLKM
LVPECL
V
i(clk)dif
differential clock input voltage peak-to-peak - 1.6 - V
Sine
V
i(clk)dif
differential clock input voltage peak-to-peak 0.8 3.0 - V
LVCMOS
V
IL
LOW-level input voltage - - 0.3V
DDA
V
V
IH
HIGH-level input voltage 0.7V
DDA
--V
Logic input: pin CTRL
V
IL
LOW-level input voltage - 0 - V
LOW-medium level - 0.3V
DDA
-V
medium-HIGH level - 0.6V
DDA
-V
V
IH
HIGH-level input voltage - V
DDA
-V
I
IL
LOW-level input current 10 - +10 A
I
IH
HIGH-level input current 10 - +10 A
Serial peripheral interface: pins CS
, SDIO/ODS, SCLK/DFS
V
IL
LOW-level input voltage 0 - 0.3V
DDA
V
V
IH
HIGH-level input voltage 0.7V
DDA
-V
DDA
V
I
IL
LOW-level input current 10 - +10 A
I
IH
HIGH-level input current 50 - +50 A
C
I
input capacitance - 4 - pF
Digital outputs, CMOS mode: pins DA11 to DA0, DB11 to DB0, OTRA, OTRB and DAV
Output levels, V
DDO
=3V
V
OL
LOW-level output voltage AGND - 0.2V
DDO
V
V
OH
HIGH-level output voltage 0.8V
DDO
-V
DDO
V
C
O
output capacitance high impedance; see Ta ble 10 -3-pF
Output levels, V
DDO
=1.8V
V
OL
LOW-level output voltage AGND - 0.2V
DDO
V
V
OH
HIGH-level output voltage 0.8V
DDO
-V
DDO
V
Table 6. Static characteristics
[1]
…continued
Symbol Parameter Conditions Min Typ Max Unit