Datasheet

ADC1212D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 4 March 2011 35 of 42
NXP Semiconductors
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
Table 28. Test pattern register 2 (address 0015h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 0 TESTPAT_USER[11:4] R/W 0000
0000
custom digital test pattern (bits 11 to 4)
Table 29. Test pattern register 3 (address 0016h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 TESTPAT_USER[3:0] R/W 0000 custom digital test pattern (bits 3 to 0)
3 to 0 - - 0000 not used
Table 30. Fast OTR register (address 0017h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 - - 0000 not used
3 FASTOTR R/W fast OuT-of-Range (OTR) detection
0 disabled
1 enabled
2 to 0 FASTOTR_DET[2:0] R/W set fast OTR detect level
000 20.56 dB
001 16.12 dB
010 11.02 dB
011 7.82 dB
100 5.49 dB
101 3.66 dB
110 2.14 dB
111 0.86 dB
Table 31. CMOS output register (address 0020h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 - - 0000 not used
3 to 2 DAV_DRV[1:0] R/W drive strength for DAV CMOS output buffer
00 low
01 medium
10 high
11 very high
1 to 0 DATA_DRV[1:0] R/W drive strength for DATA CMOS output buffer
00 low
01 medium
10 high
11 very high