Datasheet

ADC1212D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 4 March 2011 33 of 42
NXP Semiconductors
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
Table 23. Internal reference control register (address 0008h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 - - 0000 not used
3 INTREF_EN R/W programmable internal reference enable
0 disable
1 active
2 to 0 INTREF[2:0] R/W programmable internal reference
000 0dB (FS=2V)
001 1 dB (FS = 1.78 V)
010 2 dB (FS = 1.59 V)
011 3 dB (FS = 1.42 V)
100 4 dB (FS = 1.26 V)
101 5 dB (FS = 1.12 V)
110 6dB (FS=1V)
111 reserved
Table 24. Output data standard control register (address 0011h) bit description
Default values are highlighted.
Bit Symbol Access Value Description
7 to 5 - - 000 not used
4 LVDS_CMOS R/W output data standard: LVDS DDR or CMOS
0CMOS
1 LVDS DDR
3 OUTBUF R/W output buffers enable
0 output enabled
1 output disabled (high Z)
2 OUTBUS_SWAP R/W output bus swap
0 no swapping
1 output bus is swapped (MSB becomes LSB and
vice versa)
1 to 0 DATA_FORMAT[1:0] R/W output data format
00 offset binary
01 two’s complement
10 gray code
11 offset binary