Datasheet

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ADC1212D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 2 — 4 March 2011 31 of 42 NXP Semiconductors
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
11.6.3 Register allocation map
Table 19. Register allocation map
Addr
(hex)
Register name Access Bit definition Default
(bin)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0003 Channel index R/W RESERVED[5:0] ADCB ADCA 1111 1111
0005 Reset and
operating mode
R/W SW_
RST
RESERVED[2:0] - - OP_MODE[1:0] 0000 0000
0006 Clock R/W - - - SE_SEL DIFF_SE - CLKDIV DCS_EN 0000 0001
0008 Internal reference R/W - - - - INTREF_EN INTREF[2:0] 0000 0000
0011 Output data
standard.
R/W - - - LVDS_
CMOS
OUTBUF OUTBUS_SWAP DATA_FORMAT[1:0] 0000 0000
0012 Output clock R/W - - - - DAVINV DAVPHASE[2:0] 0000 1110
0013 Offset R/W - - DIG_OFFSET[5:0] 0000 0000
0014 Test pattern 1 R/W - - - - - TESTPAT_SEL[2:0] 0000 0000
0015 Test pattern 2 R/W TESTPAT_USER[11:4] 0000 0000
0016 Test pattern 3 R/W TESTPAT_USER[3:0] - - - - 0000 0000
0017 Fast OTR R/W - - - - FASTOTR FASTOTR_DET[2:0] 0000 0000
0020 CMOS output R/W - - - - DAV_DRV[1:0] DATA_DRV[1:0] 0000 1110
0021 LVDS DDR O/P 1 R/W - - RESERVED DAVI[1:0] RESERVED DATAI[1:0] 0000 0000
0022 LVDS DDR O/P 2 R/W - - - - BIT_BYTE_WISE LVDS_INT_TER[2:0] 0000 0000