Datasheet

ADC1212D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 4 March 2011 3 of 42
NXP Semiconductors
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
6. Pinning information
6.1 CMOS outputs selected
6.1.1 Pinning
6.1.2 Pin description
Fig 2. Pin configuration with CMOS digital outputs selected
ADC1212D
HVQFN64
Transparent top view
DB5
INBM
INBP
DB4
AGND DB3
VCMB DB2
REFBT DB1
REFBB DB0
AGND n.c.
CLKM n.c.
CLKP n.c.
AGND DAV
REFAB n.c.
REFAT n.c.
VCMA DA0
AGND DA1
INAM DA2
INAP DA3
VDDA VDDA
SCLK/DFS SDIO/ODS
CS
CTRL
DECB
OTRB
DB11
DB10
DB9 DB8 DB7 DB6
VDDO VDDO
VDDA VREF SENSE VDDA DECA OTRA DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 VDDO VDDO
16 33
15 34
14 35
13 36
12 37
11 38
10 39
9 40
8 41
7 42
6 43
5 44
4 45
3 46
2 47
1 48
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
terminal 1
index area
005aaa129
Table 2. Pin description (CMOS digital outputs)
Symbol Pin Type
[1]
Description
INAP 1 I analog input; channel A
INAM 2 I complementary analog input; channel A
AGND 3 G analog ground
VCMA 4 O common-mode output voltage; channel A
REFAT 5 O top reference; channel A
REFAB 6 O bottom reference; channel A
AGND 7 G analog ground
CLKP 8 I clock input
CLKM 9 I complementary clock input
AGND 10 G analog ground
REFBB 11 O bottom reference; channel B
REFBT 12 O top reference; channel B