Datasheet

ADC1212D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 4 March 2011 29 of 42
NXP Semiconductors
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
[1] Bit R/W indicates whether it is a read (logic 1) or a write (logic 0) operation.
[2] Bits W1 and W0 indicate the number of bytes to be transferred (see Table 18
).
Bits A12 to A0 indicate the address of the register being accessed. In the case of a
multiple byte transfer, this address is the first register to be accessed. An address counter
is increased to access subsequent addresses.
The steps for a data transfer:
1. A falling edge on pin CS
in combination with a rising edge on pin SCLK determine the
start of communications.
2. The first phase is the transfer of the 2-byte instruction.
3. The second phase is the transfer of the data which can vary in length but is always a
multiple of 8 bits. The MSB is always sent first (for instruction and data bytes).
4. A rising edge on pin CS
indicates the end of data transmission.
11.6.2 Default modes at start-up
During circuit initialization it does not matter which output data standard has been
selected. At power-up, the device enters Pin control mode.
A falling edge on pin CS
triggers a transition to SPI control mode. When the ADC1212D
enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by
the level on pin SDIO (see Figure 33
). Once in SPI control mode, the output data standard
can be changed via bit LVDS_CMOS
(see Table 24).
Table 17. Instruction bytes for the SPI
MSB LSB
Bit 76543210
Description R/W
[1]
W1
[2]
W0
[2]
A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
Table 18. Number of data bytes to be transferred after the instruction bytes
W1 W0 Number of bytes transmitted
001 byte
012 bytes
103 bytes
1 1 4 bytes or more
Fig 32. SPI mode timing
CS
SCLK
SDIO
R/W
W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D3 D2 D1 D0D0 D7 D6 D5 D4
Instruction bytes Register N (data) Register N + 1 (data)
005aaa086