Datasheet

ADC1212D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 4 March 2011 27 of 42
NXP Semiconductors
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
11.5.3 DAta Valid (DAV) output clock
A data valid output clock signal (DAV) is provided that can be used to capture the data
delivered by the ADC1212D. Detailed timing diagrams for CMOS and LVDS DDR modes
are provided in Figure 4
and Figure 5 respectively. In LVDS DDR mode, it is highly
recommended to shift ahead the DAV by 1 ns (bits DAVPHASE[2:0] = 0b100;
see Table 25
).
11.5.4 OuT-of-Range (OTR)
An out-of-range signal is provided on pin OTRA for ADC channel A and on pin OTRB for
ADC channel B. The latency of OTRA/OTRB is fourteen clock cycles. The OTR response
can be speeded up by enabling Fast OTR (bit FASTOTR = logic 1; see Table 30
). In this
mode, the latency of OTRA/OTRB is reduced to only four clock cycles. The Fast OTR
detection threshold (below full-scale) can be programmed via bits FASTOTR_DET[2:0].
11.5.5 Digital offset
By default, the ADC1212D delivers output code that corresponds to the analog input.
However, it is possible to add a digital offset to the output code via the SPI
(bits DIG_OFFSET[5:0]; see Table 26
).
Table 14. LVDS DDR output register 2
LVDS_INT_TER[2:0] Resistor value ()
000 no internal termination
001 300
010 180
011 110
100 150
101 100
110 81
111 6
Table 15. Fast OTR register
FASTOTR_DET[2:0] Detection level (dB)
000 20.56
001 16.12
010 11.02
011 7.82
100 5.49
101 3.66
110 2.14
111 0.86