Datasheet

ADC1212D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 4 March 2011 26 of 42
NXP Semiconductors
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
The output resistance is 50  and is the combination of an internal resistor and the
equivalent output resistance of the buffer. There is no need for an external damping
resistor. The drive strength of both DATA and DAV buffers can be programmed via the SPI
in order to adjust the rise and fall times of the output digital signals (see Table 31
).
11.5.2 Digital output buffers: LVDS DDR mode
The digital output buffers can be configured as LVDS DDR by setting bit LVDS_CMOS to
logic 1 (see Table 24
).
Each output should be terminated externally with a 100  resistor (typical) at the receiver
side (Figure 30
) or internally via SPI control bits LVDS_INT_TER[2:0] (see Figure 31 and
Table 33
).
The default LVDS DDR output buffer current is set to 3.5 mA. It can be programmed via
the SPI (bits DAVI[1:0] and DATAI[1:0]; see Table 32
) in order to adjust the output logic
voltage levels.
Fig 30. LVDS DDR digital output buffer - externally terminated
Fig 31. LVDS DDR digital output buffer - internally terminated
DAn_DAn + 1_M; DBn_DBn + 1_M
VDDO
3.5 mA
typical
AGND
100 Ω
-
005aaa112
+
-
+
RECEIVER
DAn_DAn + 1_P; DBn_DBn + 1_P
DAn_DAn + 1_P; DBn_DBn + 1_P
DAn_DAn + 1_M; DBn_DBn + 1_M
VDDO
3.5 mA
typical
AGND
100 Ω
-
005aaa113
+
-
+
RECEIVER
100 Ω