Datasheet

ADC1212D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 4 March 2011 24 of 42
NXP Semiconductors
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
11.4.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in Figure 28. The common-mode
voltage of the differential input stage is set via internal 5 k resistors.
a. Sine clock input b. Sine clock input (with transformer)
c. LVPECL clock input
Fig 27. Differential clock input
Sine
clock input
CLKP
CLKM
005aaa173
Sine
clock input
CLKP
CLKM
005aaa054
LVPECL
clock input
005aaa172
CLKP
CLKM
V
cm(clk)
= common-mode voltage of the differential input stage
Fig 28. Equivalent input circuit
CLKP
CLKM
005aaa056
Package ESD Parasitics
5 kΩ 5 kΩ
V
cm(clk)
SE_SEL SE_SEL