Datasheet

ADC1212D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 4 March 2011 23 of 42
NXP Semiconductors
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
11.3.4 Biasing
The common-mode input voltage (V
I(cm)
) on pins INAP/INBP and INAM/INBM should be
set externally to 0.5V
DDA
for optimal performance and should always be between 0.9 V
and 2 V (see Table 6
).
11.4 Clock input
11.4.1 Drive modes
The ADC1212D can be driven differentially (LVPECL). It can also be driven by a
single-ended LVCMOS signal connected to pin CLKP (pin CLKM should be connected to
ground via a capacitor) or pin CLKM (pin CLKP should be connected to ground via a
capacitor).
Fig 25. Equivalent schematic of the common-mode reference circuit
1.5 V
VCMA/VCMB
0.1 μF
Package ESD Parasitics
005aaa099
COMMON MODE
REFERENCE
ADC CORE
a. Rising edge LVCMOS b. Falling edge LVCMOS
Fig 26. LVCMOS single-ended clock input
LVCMOS
clock input
CLKP
CLKM
005aaa174
005aaa053
LVCMOS
clock input
CLKP
CLKM