Datasheet

ADC1212D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 4 March 2011 2 of 42
NXP Semiconductors
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
4. Ordering information
5. Block diagram
Table 1. Ordering information
Type number f
s
(Msps) Package
Name Description Version
ADC1212D125HN/C1 125 HVQFN64 plastic thermal enhanced very thin quad flat package;
no leads; 64 terminals; body 9  9  0.85 mm
SOT804-3
ADC1212D105HN/C1 105 HVQFN64 plastic thermal enhanced very thin quad flat package;
no leads; 64 terminals; body 9  9  0.85 mm
SOT804-3
ADC1212D080HN/C1 80 HVQFN64 plastic thermal enhanced very thin quad flat package;
no leads; 64 terminals; body 9  9  0.85 mm
SOT804-3
ADC1212D065HN/C1 65 HVQFN64 plastic thermal enhanced very thin quad flat package;
no leads; 64 terminals; body 9  9  0.85 mm
SOT804-3
Fig 1. Block diagram
ADC1212D
SPI INTERFACE
OUTPUT
DRIVERS
OUTPUT
DRIVERS
SYSTEM
REFERENCE AND
POWER
MANAGEMENT
ERROR
CORRECTION AND
DIGITAL
PROCESSING
ADC CORE
12-BIT
PIPELINED
T/H
INPUT
STAGE
INAP
CS
SDIO/ODS
SCLK/DFS
OTRA
OTRB
CTRL
REFAT
REFAB
REFBB
REFBT
CMOS:
DA11 to DA0
or
LVDS/DDR:
DA10_DA11_P to DA0_DA1_P,
DA10_DA11_M to DA0_DA1_M
CMOS:
DB11 to DB0
or
LVDS/DDR:
DB10_DB11_P to DB0_DB1_P,
DB10_DB11_M to DB0_DB1_M
INAM
CLKP
CLKM
CLOCK INPUT
STAGE AND DUTY
CYCLE CONTROL
VCMA
VREF
SENSE
VCMB
OUTPUT
DRIVERS
ADC CORE
12-BIT
PIPELINED
T/H
INPUT
STAGE
INBP
INBM
ERROR
CORRECTION AND
DIGITAL
PROCESSING
CMOS:
DAV
or
LVDS/DDR:
DAVP
DAVM
005aaa128