Datasheet

ADC1212D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 4 March 2011 18 of 42
NXP Semiconductors
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
11.1.4 Selecting the output data format
The output data format can be selected via the SPI interface (offset binary,
two’s complement or gray code; see Table 24
) or by using pin DFS in Pin control mode
(offset binary or two’s complement). Offset binary is selected when DFS is LOW. When
DFS is HIGH, two’s complement is selected.
11.2 Analog inputs
11.2.1 Input stage
The analog input of the ADC1212D supports a differential or a single-ended input drive.
Optimal performance is achieved using differential inputs with the common-mode input
voltage (V
I(cm)
) on pins INAP, INAM, INBP and INBM set to 0.5V
DDA
.
The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
via a programmable internal reference (see Section 11.3
and Table 23).
The equivalent circuit of the sample-and-hold input stage, including ElectroStatic
Discharge (ESD) protection and circuit and package parasitics, is shown in Figure 16
.
The sample phase occurs when the internal clock (derived from the clock signal on pin
CLKP/CLKM) is HIGH. The voltage is then held on the sampling capacitors. When the
clock signal goes LOW, the stage enters the hold phase and the voltage information is
transmitted to the ADC core.
11.2.2 Anti-kickback circuitry
Anti-kickback circuitry (RC filter in Figure 17 is needed to counteract the effects of charge
injection generated by the sampling capacitance.
The RC filter is also used to filter noise from the signal before it reaches the sampling
stage. The value of the capacitor should be chosen to maximize noise attenuation without
degrading the settling time excessively.
Fig 16. Input sampling circuit
005aaa092
INAP/INBP
Package ESD Parasitics
Switch
R
on
= 14 Ω
4 pF
4 pF
Sampling
capacitor
Sampling
capacitor
Switch
R
on
= 14 Ω
INAM/INBM
internal
clock
internal
clock