Datasheet

ADC1212D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 4 March 2011 17 of 42
NXP Semiconductors
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
11. Application information
11.1 Device control
The ADC1212D can be controlled via the Serial Peripheral Interface (SPI control mode) or
directly via the I/O pins (Pin control mode).
11.1.1 SPI and Pin control modes
The device enters Pin control mode at power-up and remains in this mode as long as pin
CS
is held HIGH. In Pin control mode, the SPI pins SDIO, CS and SCLK are used as
static control pins.
SPI control mode is enabled by forcing pin CS
LOW. Once SPI control mode has been
enabled, the device remains in this mode. The transition from Pin control mode to SPI
control mode is illustrated in Figure 15
.
When the device enters SPI control mode, the output data standard and data format are
determined by the level on pin SDIO as soon as a transition is triggered by a falling edge
on CS
.
11.1.2 Operating mode selection
The active ADC1212D operating mode (Power-up, Power-down or Sleep) can be selected
via the SPI interface (see Table 21
) or by using pin CTRL in Pin control mode, as
described in Table 10
.
11.1.3 Selecting the output data standard
The output data standard (CMOS or LVDS DDR) can be selected via the SPI interface
(see Table 24
) or by using pin ODS in Pin control mode. LVDS DDR is selected when
ODS is HIGH, otherwise CMOS is selected.
Fig 15. Control mode selection.
R/W
SPI control mode
Pin control mode
Data format
offset binary
Data format
two's complement
LVDS DDR
SDIO/ODS
SCLK/DFS
W1 W0 A12
005aaa039
CMOS
CS
Table 10. Operating mode selection via pin CTRL
Pin CTRL Operating mode Output high-Z
0 Power-down yes
0.3V
DDA
Sleep yes
0.6V
DDA
Power-up yes
V
DDA
Power-up no