Datasheet

ADC1212D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 4 March 2011 13 of 42
NXP Semiconductors
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
t
clk
=1/f
clk
Fig 4. CMOS mode timing
t
clk
=1/f
clk
Fig 5. LVDS DDR mode timing
(N − 12)
t
d(s)
t
clk
N N + 1
N + 2
t
clk
t
su
t
PD
t
h
t
PD
CLKP
CLKM
DATA
DAV
005aaa060
(N − 11)(N − 13)(N − 14)
005aaa114
(N − 14)
t
d(s)
t
clk
N N + 1
N + 2
CLKP
CLKM
DAVP
DAVM
t
PD
(N − 11)(N − 12)(N − 13)
DA
x
/
DB
x
DA
x
/
DB
x
DA
x
/
DB
x
DA
x
/
DB
x
DA
x+1/
DB
x+1
DA
x+1/
DB
x+1
DA
x+1/
DB
x+1
DA
x+1/
DB
x+1
DA
x+1/
DB
x+1
DA
x
_
DA
x + 1
_
P/
DB
x
_
DB
x + 1
_
P
DA
x
_
DA
x + 1
_
M/
DB
x
_
DB
x + 1
_
M
DA
x
/
DB
x
t
PD
t
clk
t
h
t
su
t
h
t
su