Datasheet
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ADC1212D_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 4 March 2011 12 of 42
NXP Semiconductors
ADC1212D series
Dual 12-bit ADC: CMOS or LVDS DDR digital outputs
[1] Typical values measured at V
DDA
=3V, V
DDO
=1.8V,
Tamb
=25C; minimum and maximum values are across the full temperature range T
amb
= 40 Cto +85C at V
DDA
=3V,
V
DDO
= 1.8 V; V
INAP
V
INAM
= 1 dBFS; V
INBP
V
INBM
= 1 dBFS; unless otherwise specified.
[2] Measured between 20 % to 80 % of V
DDO
.
[3] Rise time measured from 50 mV to +50 mV; fall time measured from +50 mV to 50 mV.
LVDS DDR mode timing: pins DA10_DA11_P to DA0_DA1_P, DA10_DA11_M to DA0_DA1_M, DB10_DB11_P to DB0_DB1_P,
DB10_DB11_M to DB0_DB1_M; DAVP and DAVM
t
PD
propagation delay DATA - 3.9 - - 3.9 - - 3.9 - - 3.9 - ns
DAV - 4.2 - - 4.2 - - 4.2 - - 4.2 - ns
t
su
set-up time - 5.1 - - 3.5 - - 2.1 - - 1.4 - ns
t
h
hold time - 2.0 - - 2.0 - - 2.0 - - 2.0 - ns
t
r
rise time DATA
[3]
50 100 200 50 100 200 50 100 200 50 100 200 ps
DAV 50 100 200 50 100 200 50 100 200 50 100 200 ps
t
f
fall time DATA
[3]
50 100 200 50 100 200 50 100 200 50 100 200 ps
DAV 50 100 200 50 100 200 50 100 200 50 100 200 ps
Table 8. Clock and digital output timing characteristics
[1]
…continued
Symbol Parameter Conditions ADC1212D065 ADC1212D080 ADC1212D105 ADC1212D125 Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max