Datasheet

NXP Semiconductors
Quick start ADC1415S, ADC1215S, ADC1115S, ADC1015S series (F1 or
F2 versions)
Quick start
© NXP B.V. 2011. All rights reserved. © NXP B.V. 2011. All rights reserved.
Quick start Rev. 5 — January 2011 6 of 28
Table 2. Input signals
Name Function View
J1 IN connector – Analog input signal (
50
Ω
matching)
J2 CLKP connector – Single ended clock input signal (
50
Ω
matching), with a transformer.
J3 CLKM connector – Grounded on that demoboard
1.5 Output signals in CMOS version (D0 to D1x, DAV, OTR)
The digital output signal is available in binary, 2’s complement or gray format.
A Data Valid Output clock (DAV) is provided by the device for the data acquisition.
Table 3. Output signals
Name Function View
J6 Array connector – ADC digital output (D0 to D1x), OTR
and Data Valid (DAV)
J6
J1
J2
J3