Quick start ADC1415S, ADC1215S, ADC1115S, ADC1015S series (F1 or F2 versions) Demonstration board for ADC1415S, A ADC1215S, DC1215S, ADC1115S, ADC1015S series Rev. 5 — January 2011 Quick start Document information Info Content Keywords PCB2122-2, Demonstration board, ADC, Converter Abstract This document describes how to use the demonstration board for the analog-to-digital converter ADC1415S, ADC1215S, ADC1115S, ADC1015S series.
Quick start ADC1415S, ADC1215S, ADC1115S, ADC1015S series (F1 or F2 versions) NXP Semiconductors Quick start Revision history Rev Date Description 1 20081001 Initial version. 2 20090518 Update 3 20090610 Add SPI software description. 4 20100519 Add HSDC extension module acquisition system description. 5 20110120 Update with latest software tool.
NXP Semiconductors Quick start 1. Overview of the ADC1x15S demo board 1.1 ADC1415S, ADC1215S, ADC1115S, ADC1015S F1 series (CMOS digital outputs) Figure below presents the connections to measure ADC161xS. USB SPI Register programming DC adaptor connected to mains LOGIC ANALYZER SYNTHESIZED SIGNAL GENERATOR INPUT SIGNAL . 2Vpp sine wave . AC FILTER . High-order . Band pass SYNTHESIZED SIGNAL GENERATOR CLOCK SIGNAL . Sine wave . AC 3 of 28 Quick start Fig 1. 1.
NXP Semiconductors Quick start 1.2 ADC1415S, ADC1215S, ADC1115S, ADC1015S F2 series (LVDS/DDR digital outputs) Figure below presents the connections to measure ADC1x15S. USB SPI Register programming DC adaptor connected to mains SYNTHESIZED SIGNAL GENERATOR INPUT SIGNAL . 2Vpp sine wave . AC FILTER . High-order . Band pass SYNTHESIZED SIGNAL GENERATOR CLOCK SIGNAL . Sine wave . AC Quick start 4 of 28 Fig 2. ADC1415S, ADC1215S, ADC1115S, ADC1015S setup PRESENTED CONFIGURATION CONFIGURATI .
NXP Semiconductors Quick start ADC1415S, ADC1215S, ADC1115S, ADC1015S series (F1 or F2 versions) Quick start 1.3 Power supply The e board is powered either with a 3 VDC and 1.8/3 VDC power supplies or a 5V DC adaptor. Table 1. Power supply Name Function View J8 2.1 Jack connector – 5VDC J10 / J11 Change ST9 and ST10 position accordingly J8 TP1 J10 +3V green connector – Power supply 3 VDC J11 Change ST9 and ST10 position accordingly ST9/10 CMOS version +1.8V green connector – Power supply 1.
NXP Semiconductors Quick start ADC1415S, ADC1215S, ADC1115S, ADC1015S series (F1 or F2 versions) Quick start Table 2. Input signals Name Function View J1 IN connector – Analog input signal (50Ω matching) J2 CLKP connector – Single ended clock input signal (50Ω matching), with a transformer. J3 CLKM connector – Grounded on that demoboard J1 J3 J2 1.5 Output signals in CMOS version (D0 to D1x, DAV, OTR) The digital output signal is available in binary, 2’s complement or gray format.
NXP Semiconductors Quick start ADC1415S, ADC1215S, ADC1115S, ADC1015S series (F1 or F2 versions) Quick start 1.6 Output signals in LVDS DDR version The digital output signal is available in binary, 2’s complement or gray format. A Data Valid Output clock (DAV) is provided by the device for the data acquisition. Table 4. Output signals Name Function View J7 Samtec QTH connector – ADC digital output (D0 to D1x) and Data Valid (DAV) J7 © NXP B.V. 2011. All rights reserved. Quick start Rev.
NXP Semiconductors Quick start ADC1415S, ADC1215S, ADC1115S, ADC1015S series (F1 or F2 versions) Quick start 1.7 SPI Mode The ADC1x15S can be controlled either by a Serial Peripheral Interface (SPI) or by PIN. Table 5. SPI Interface Name Function View J12 USB connector – SPI interface J12 1.8 SPI program For more details on how to control device with SPI, refer to section 3.3. © NXP B.V. 2011. All rights reserved. Quick start Rev.
NXP Semiconductors Quick start 2. HSDC extension module: acquisition board The figure 4 shows an overview of the extension module HSDC-EXTMOD01/DB acquisition board: RED LED FOR +3V3 POWER RED LED FOR POWER SUPPLY CONNECTION +5V POWER SUPPLY . I = 3.2 A SIGNAL GENERATOR Rev. 5 — January 2011 REFERENCE SIGNAL . Typical 10 MHz GREEN LED FOR EMBEDDED PLL LOCK STATUS CMOS I/O CONNECTOR .
NXP Semiconductors Quick start ADC1415S, ADC1215S, ADC1115S, ADC1015S series (F1 or F2 versions) Quick start The HSDC extension module is intended for acquisition/generation and clock generation purpose. When connected to an ADC demo-board it is intended as an acquisition system for digital output bits delivered by ADC, either CMOS (HE14 P1 connector) or LVDS DDR (SAMTEC QTH_060_02 P2 connector).
NXP Semiconductors Quick start ADC1415S, ADC1215S, ADC1115S, ADC1015S series (F1 or F2 versions) Quick start Fig 4. HSDC extension module: HE14 CMOS hardware schematic overview © NXP B.V. 2011. All rights reserved. Quick start Rev.
NXP Semiconductors Quick start 3. Combo 1x15S and HSDC extension module 3.1 ADC1415S, ADC1215S, ADC1115S, ADC1015S setup CMOS outputs The figure 24 below shows an overview of the whole system ADC1x15S+HSDC extension module with CMOS outputs configuration for which connection is straightforward, together with a supply extension module (release A) for the ADC1x15S demo-board: USB SPI MODULE +5V POWER SUPPLY . I = 3.2A Rev. 5 — January 2011 SIGNAL GENERATOR REFERENCE SIGNAL . E.g.
NXP Semiconductors Quick start 3.2 ADC1415S, ADC1215S, ADC1115S, ADC1015S setup LVDS/DDR outputs The figure 24 below shows an overview of the whole system ADC1x15S+HSDC extension module with CMOS outputs configuration for which connection is straightforward, together with a supply extension module (release A) for the ADC1x15S demo-board: USB SPI MODULE +5V POWER SUPPLY . I = 3.2A USB SPI MODULE REFERENCE SIGNAL . E.g. 170MHz CLOCK GENERATOR CLOCK SIGNAL . E.g. 122.88MHz +5V POWER SUPPLY . I = 3.
Quick start ADC1415S, ADC1215S, ADC1115S, ADC1015S series (F1 or F2 versions) NXP Semiconductors Quick start 3.3 ADC Software tool Run the application “SW_ADC_1_r02.exe”. This application will allow: • the user to control features on our high speed ADC through the SPI interface available on any ADC1415S, ADC1215S, ADC1115S, ADC1015S series; • As well as performing any online data acquisition to evaluate the performances of the ADC1415S, ADC1215S, ADC1115S, ADC1015S series.
NXP Semiconductors Quick start ADC1415S, ADC1215S, ADC1115S, ADC1015S series (F1 or F2 versions) Quick start Fig 8. SW_ADC_1_r02: “Info” page The HSDC-EXTMOD is not yet initialized, so the embedded PLL (LMK03001 in this example) is not locked. Initialization is only required for acquisition purpose. © NXP B.V. 2011. All rights reserved. Quick start Rev.
NXP Semiconductors Quick start ADC1415S, ADC1215S, ADC1115S, ADC1015S series (F1 or F2 versions) Quick start 3.3.1 ADC SPI programming Functional Registers page The page displays all SPI registers for ADC1115S series: Fig 9. SW_ADC_1_r02: “ADC - Functional Registers” page Perform any settings and then click on the “Send data to device” button to update the device registers. © NXP B.V. 2011. All rights reserved. Quick start Rev.
Quick start ADC1415S, ADC1215S, ADC1115S, ADC1015S series (F1 or F2 versions) NXP Semiconductors Quick start 3.3.2 ADC SPI programming Read Registers page This page can be used to read all registers by clicking on the “Read all registers” button and will display the result in the table below: Fig 10. SW_ADC_1_r02: “ADC - Read Registers” page When all registers have been read, it is possible to save the data to a text file. The settings are saved in a table-like format as shown below: Table 6.
Quick start ADC1415S, ADC1215S, ADC1115S, ADC1015S series (F1 or F2 versions) NXP Semiconductors Quick start Column 1 Column 2 20 0e 21 00 22 00 Note that all data are saved in hexadecimal format. Click on the “Save registers read to file” button to select the file to store data to. Make sure that you store your file with “.txt” extension, this will allow you to re-use the file on the “ADC - Load Registers” page. 3.3.
NXP Semiconductors Quick start ADC1415S, ADC1215S, ADC1115S, ADC1015S series (F1 or F2 versions) Quick start 3.3.4 Tools page This page allows the user to calculate the coherent frequencies values involved of the acquisition process. It gives an indication where the 6 first harmonics are located in the Nyquist zone. Enter your analog and sampling frequencies in field . Indicate the number of samples to be acquired , as well as the fixed parameter for the coherency calculation (Fs in our example above ).
Quick start ADC1415S, ADC1215S, ADC1115S, ADC1015S series (F1 or F2 versions) NXP Semiconductors Quick start 3.3.5 Acquisition page This page will acquire data to evaluate the high dynamic performance of the device: Fig 13. SW_ADC_1_r02: “Acquisition” page Before proceeding to any acquisition, the user needs to do the following entries: • the sampling frequency Fs: 122.
Quick start ADC1415S, ADC1215S, ADC1115S, ADC1015S series (F1 or F2 versions) NXP Semiconductors Quick start Table 7. Dynamic results as stored in a text file Content of file is shown as table format Name Fin Fs Vin ENOB SINAD_C SNR_C SNR_FS SFDR_C SFDR_FS THD H2 H3 H4 H5 H6 (MHz) (MHz) (dBFS) - (dBc) (dBc) (dBFS) (dBc) (dBFS) (dBc) (dBc) (dBc) (dBc) (dBc) (dBc) 5.00 122.86 -0.93 10.53 65.30 65.18 66.23 81.82 82.75 -81.02 -98.65 -82.75 -102.16 -90.69 -108.
NXP Semiconductors Quick start ADC1415S, ADC1215S, ADC1115S, ADC1015S series (F1 or F2 versions) Quick start 3.3.5.2 Reorganized signal The reorganized signal displays the reconstructed sine wave from coherency calculation corresponding to 1 period of the input signal: Fig 15. SW_ADC_1_r02: “Acquisition” page, reorganized signal graph Press the “Autoscale” button to display the whole content. © NXP B.V. 2011. All rights reserved. Quick start Rev.
NXP Semiconductors Quick start ADC1415S, ADC1215S, ADC1115S, ADC1015S series (F1 or F2 versions) Quick start 3.3.5.3 Unreconstructed signal The unreconstructed signal displays the unreconstructed sine wave corresponding to the whole number of period being acquired following the coherency rule: Zoom tool Fig 16. SW_ADC_1_r02: “Acquisition” page, unreconstructed signal graph Press the “Autoscale” button to display the whole content. Use the zoom tool to observe in more details all the captured data.
NXP Semiconductors Quick start ADC1415S, ADC1215S, ADC1115S, ADC1015S series (F1 or F2 versions) Quick start 3.3.5.4 Histogram The histogram graph shows the distribution of output codes. This graph shows which code is present and if there is any missing code in the conversion range: Fig 17. SW_ADC_1_r02: “Acquisition” page, code histogram graph Press the “Autoscale” button to display the whole content. The table shows the range of output codes. © NXP B.V. 2011. All rights reserved. Quick start Rev.
NXP Semiconductors Quick start ADC1415S, ADC1215S, ADC1115S, ADC1015S series (F1 or F2 versions) Quick start 3.3.6 Info page This page will give practical information related to software and hardware settings: Fig 18.
NXP Semiconductors Quick start ADC1415S, ADC1215S, ADC1115S, ADC1015S series (F1 or F2 versions) Quick start 4. Appendix A.1: coherency calculation The coherency relies on the fact that clock and analog input signal are synchronized and the first and last samples being captured are adjoining samples: it ensures a continuous digitized time process for the FFT processing.
NXP Semiconductors Quick start ADC1415S, ADC1215S, ADC1115S, ADC1015S series (F1 or F2 versions) Quick start 5. Notes For any question, feel free to contact us at the following e-mail dataconverter-support@nxp.com. © NXP B.V. 2011. All rights reserved. Quick start Rev.
NXP Semiconductors Quick start ADC1415S, ADC1215S, ADC1115S, ADC1015S series (F1 or F2 versions) Quick start 6. Contents 1. 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 2. 2.1 2.2 3. 3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 4. 5. 6. Overview of the ADC1x15S demo board ................................................................................................................. 3 ADC1415S, ADC1215S, ADC1115S, ADC1015S F1 series (CMOS digital outputs) ...............................................
