Datasheet

ADC1113D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 10 February 2011 34 of 41
NXP Semiconductors
ADC1113D125
Dual 11-bit ADC; serial JESD204A interface
0 LANE_PD R/W lane power-down control:
0 lane is operational
1 lane is in Power-down mode
Table 50. Lane0_0_ctrl (address 0870h)
…continued
Default values are highlighted.
Bit Symbol Access Value Description
Table 51. Lane2_0_ctrl (address 0871h)
Default values are highlighted.
Bit Symbol Access Value Description
7 - - 0 not used
6 SCR_IN_MODE R/W defines the input type for scrambler and 8b/10b units:
0 (reset) (normal mode) = input of the scrambler and 8b/10b units is
the output of the Frame Assembly unit.
1 input of the scrambler and 8b/10b units is the PRBS generator
(PRBS type is defined with “PRBS_TYPE” (Ser_PRBS_Ctrl
register)
5 to 4 LANE_MODE[1:0] R/W defines output type of lane output unit:
00 (reset) normal mode: lane output is the 8-bit/10-bit output unit
01 constant mode: lane output is set to a constant (0x0)
10 toggle mode: lane output is toggling between 0x0 and 0x1
11 PRBS mode: lane output is the PRBS generator (PRBS type is
defined with “PRBS_TYPE” (Ser_PRBS_Ctrl register)
3 - - 0 not used
2 LANE_POL R/W defines lane polarity:
0 lane polarity is normal
1 lane polarity is inverted
1 LANE_CLK_POS_EDGE R/W defines lane clock polarity:
0 lane clock provided to the serializer is active on positive
edge
1 lane clock provided to the serializer is active on negative edge
0 Lane_PD R/W lane power-down control:
0 lane is operational
1 lane is in Power-down mode