Datasheet

ADC1113D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 10 February 2011 32 of 41
NXP Semiconductors
ADC1113D125
Dual 11-bit ADC; serial JESD204A interface
Table 40. Cfg_5_K (address 0824h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 5 - - 000 not used
4 to 0 K[4:0] R/W 01000 defines the number of frames per multiframe, minus 1
Table 41. Cfg_6_M (address 0825h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 1 - - 0000000 not used
0 M R/W 0 defines the number of converters per device, minus 1
Table 42. Cfg_7_CS_N (address 0826h)
Default values are highlighted.
Bit Symbol Access Value Description
7 - - 0 not used
6 CS[0] R/W 1 defines the number of control bits per sample, minus 1
5 to 4 - - 00 not used
3 to 0 N[3:0] R/W 0001 defines the converter resolution
Table 43. Cfg_8_Np (address 0827h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 5 - - 000 not used
4 to 0 NP[4:0] R/W 01111 defines the total number of bits per sample, minus 1
Table 44. Cfg_9_S (address 0828h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 1 - - 0000000 not used
0S R/W0 defines number of samples per converter per frame cycle
Table 45. Cfg_10_HD_CF (address 0829h)
Default values are highlighted.
Bit Symbol Access Value Description
7 HD R/W 0 defines high density format
6 to 2 - - 00000 not used
1 to 0 CF[1:0] R/W 00 defines number of control words per frame clock cycle per link.
Table 46. Cfg_01_2_LID (address 082Ch)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 5 - - 000 not used
4 to 0 LID[4:0] R/W 11011 defines lane 1 identification number