Datasheet

ADC1113D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 10 February 2011 31 of 41
NXP Semiconductors
ADC1113D125
Dual 11-bit ADC; serial JESD204A interface
Table 33. Ser_ScramblerA (address 0809h)
Default values are highlighted.
Bit Symbol Access Value Description
7 - - 0 not used
6 to 0 LSB_INIT[6:0] R/W 0000000 defines the initialization vector for the scrambler polynomial
(lower)
Table 34. Ser_ScramblerB (address 080Ah)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 0 MSB_INIT[7:0] R/W 11111111 defines the initialization vector for the scrambler polynomial
(upper)
Table 35. Ser_PRBS_Ctrl (address 080Bh)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 2 - - 000000 not used
1 to 0 PRBS_TYPE[1:0] R/W defines the type of Pseudo-Random Binary Sequence (PRBS)
generator to be used:
00 (reset) PRBS-7
01 PRBS-7
10 PRBS-23
11 PRBS-31
Table 36. Cfg_0_DID (address 0820h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 0 DID[7:0] R 11101101 defines the device (= link) identification number
Table 37. Cfg_1_BID (address 0821h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 - - 0000 not used
3 to 0 BID[3:0] R/W 1010 defines the bank ID – extension to DID
Table 38. Cfg_3_SCR_L (address 0822h)
Default values are highlighted.
Bit Symbol Access Value Description
7 SCR R/W 0 scrambling enabled
6 to 1 - - 000000 not used
0 L R/W 0 defines the number of lanes per converter device, minus 1
Table 39. Cfg_4_F (address 0823h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 3 - - 00000 not used
2 to 0 F[2:0] R/W 001 defines the number of octets per frame, minus 1