Datasheet

ADC1113D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 10 February 2011 30 of 41
NXP Semiconductors
ADC1113D125
Dual 11-bit ADC; serial JESD204A interface
Table 30. Ser_Control1 (address 0805h)
Default values are highlighted.
Bit Symbol Access Value Description
7 - - 0 not used
6 TRISTATE_CFG_PINS R/W 1 pins CFG3 to CFG0 are set to high-impedance. Switch to 0
automatically after start-up or reset.
5 SYNC_POL R/W defines the sync signal polarity:
0 synchronization signal is active LOW
1 synchronization signal is active HIGH
4 SYNC_SINGLE_ENDED R/W defines the input mode of the sync signal:
0 synchronization input mode is set in Differential mode
1 synchronization input mode is set in Single-ended mode
3 - - 1 not used
2 REV_SCR - LSBs are swapped with MSBs at the scrambler input:
0 disable
1 enable
1 REV_ENCODER - LSBs are swapped with MSBs at the 8-bit/10-bit encoder input:
0 disable
1 enable
0 REV_SERIAL - LSBs are swapped with MSBs at the lane input:
0 disable
1enable
Table 31. Ser_Control2 (address 0806h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 2 - - 000000 not used
1 SWAP_LANE_1_2 R/W outputs of the JESD204A unit are swapped. (Output buffer A is
connected to Lane 1, Output buffer B is connected to Lane 0):
0 disable
1enable
0 SWAP_ADC_0_1 R/W inputs of the JESD204A unit are swapped. (ADC A output is
connected to Input B, ADC B is connected to Input A):
0 disable
1enable
Table 32. Ser_Analog_Ctrl (address 0808h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 3 - - 00000 not used
2 to 0 SWING_SEL[2:0] R/W 011 defines the swing of output buffers A and B