Datasheet

ADC1113D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 10 February 2011 3 of 41
NXP Semiconductors
ADC1113D125
Dual 11-bit ADC; serial JESD204A interface
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 2. Pinning diagram
005aaa166
ADC1113D
Transparent top view
DGND
INBM
INBP
DGND
VCMB VDDD
REFBT CMLPB
REFBB CMLNB
AGND VDDD
CLKM DGND
CLKP DGND
AGND VDDD
REFAB CMLNA
REFAT CMLPA
VCMA VDDD
INAM DGND
INAP DGND
VDDA VDDA
SCLK
SDIO
CS
AGND
RESET
SCRAMBLER
CFG0 CFG1 CFG2 CFG3
VDDD
DGND
VDDA VREF SENSE VDDA AGND AGND VDDA DNC SWING_1 SWING_0 VDDD DGND SYNCN SYNCP
14 29
13 30
12 31
11 32
10 33
9 34
8 35
7 36
6 37
5 38
4 39
3 40
2 41
1 42
15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43
Table 2. Pin description
Symbol Pin Type
[1]
Description
INAP 1 I channel A analog input
INAM 2 I channel A complementary analog input
VCMA 3 O channel A output common voltage
REFAT 4 O channel A top reference
REFAB 5 O channel A bottom reference
AGND 6 G analog ground
CLKP 7 I clock input
CLKM 8 I complementary clock input
AGND 9 G analog ground
REFBB 10 O channel B bottom reference
REFBT 11 O channel B top reference
VCMB 12 O channel B output common voltage
INBM 13 I channel B complementary analog input