Datasheet

ADC1113D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 10 February 2011 29 of 41
NXP Semiconductors
ADC1113D125
Dual 11-bit ADC; serial JESD204A interface
[1] F: Octets per frame clock cycle
HD: High-density mode
K: Frame per multi-frame
M: Converters per device
L: Lane per converter device
CS: Number of control bits per conversion sample
CF: Control words per frame clock cycle and link
S: Number of samples transmitted per single converter per frame cycle
Table 28. Ser_Cfg_Setup (address 0803h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 4 - - 0000 not used
3 to 0 CFG_SETUP[3:0] R/W 1000 quick configuration of JESD204A. These settings overrule the
configuration of pins CFG3 to CFG0 (see Table 29
).
Table 29. JESD204A configuration table
CFG_SETUP[3:0] ADC A ADC B Lane 0 Lane 1 F
[1]
HD
[1]
K
[1]
M
[1]
L
[1]
Comment CS
[1]
CF
[1]
S
[1]
00000ON ON ON ON 20922(F× K) ≥ 17 1 0 1
10001ON ON ON OFF 3 0 6 2 1 (F × K) ≥ 17 1 0 1
20010ON ON OFF ON 30621(F× K) ≥ 17 1 0 1
30011ON OFF ON ON 111712(F× K) ≥ 17 1 0 1
40100OFFON ON ON 111712(F× K) ≥ 17 1 0 1
50101ON OFF ON OFF 2 0 9 1 1 (F × K) ≥ 17 1 0 1
60110ON OFF OFF ON 20911(F× K) ≥ 17 1 0 1
70111OFFON ON OFF 2 0 9 1 1 (F × K) ≥ 17 1 0 1
81000OFFON OFF ON 20911(F× K) ≥ 17 1 0 1
9 1001 reserved
10 1010 reserved
11 1011 reserved
12 1100 reserved
13 1101 reserved
14 1110 ON ON ON ON 2 0 9 2 2 test: loop
alignment
101
15 1111 OFF OFF OFF OFF 2 0 9 2 2 chip
power-down
101