Datasheet

ADC1113D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 10 February 2011 28 of 41
NXP Semiconductors
ADC1113D125
Dual 11-bit ADC; serial JESD204A interface
11.6.4 JESD204A digital control registers
Table 24. Register Test pattern 2 (address 0015h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 0 TESTPAT_2[10:3] R/W 00000000 custom digital test pattern (bit 10 to 3)
Table 25. Register Test pattern 3 (address 0016h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 0 TESTPAT_3[2:0] R/W 00000000 custom digital test pattern (bit 2 to 0)
Table 26. Ser_Status (address 0801h)
Default values are highlighted.
Bit Symbol Access Value Description
7 RXSYNC_ERROR R 0 set to 1 when a synchronization error occurs
6 to 4 RESERVED[2:0] - 001 reserved
3 to 2 - - 0 not used
1POR_TST R 0 power-on-reset
0 RESERVED - 0 reserved
Table 27. Ser_Reset (address 0802h)
Default values are highlighted.
Bit Symbol Access Value Description
7SW_RST R/W0 initiates a software reset of the JESD204A unit
6 to 4 - - 000 not used
3FSM_SW_RSTR/W0 initiates a software reset of the internal state machine of
JESD204A unit
2 to 0 - - 000 not used