Datasheet

ADC1113D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 10 February 2011 26 of 41
NXP Semiconductors
ADC1113D125
Dual 11-bit ADC; serial JESD204A interface
11.6.3 Register description
11.6.3.1 ADC control registers
Table 18. Register Channel Index (address 0003h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 2 - - 111111 not used
1 ADCB R/W ADC B gets the next SPI command:
0ADCB not selected
1 ADC B selected
0 ADCA R/W ADC A gets the next SPI command:
0 ADC A not selected
1 ADC A selected
Table 19. Register Reset and Power-down mode (address 0005h)
Default values are highlighted.
Bit Symbol Access Value Description
7 SW_RST R/W reset digital part:
0 no reset
1 performs a reset of the digital part
6 to 2 - - 00000 not used
1 to 0 PD[1:0] R/W power-down mode:
00 normal (power-up)
01 full power-down
10 sleep
11 normal (power-up)
Table 20. Register Clock (address 0006h)
Default values are highlighted.
Bit Symbol Access Value Description
7 to 5 - - 000 not used
4 SE_SEL R/W select SE clock input pin:
0 select CLKM input
1 select CLKP input
3 DIFF_SE R/W differential/single-ended clock input select:
0 fully differential
1 single-ended
2 - - 0 not used
1 CLKDIV2_SEL R/W select clock input divider by 2:
0 disable
1 active
0 DCS_EN R/W duty cycle stabilizer enable:
0 disable
1 active