Datasheet

ADC1113D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 10 February 2011 22 of 41
NXP Semiconductors
ADC1113D125
Dual 11-bit ADC; serial JESD204A interface
11.6 Serial Peripheral Interface (SPI)
11.6.1 Register description
The ADC1113D125 serial interface is a synchronous serial communications port allowing
for easy interfacing with many industry microprocessors. It provides access to the
registers that control the operation of the chip in both read and write modes.
This interface is configured as a 3-wire type (SDIO as bidirectional pin).
SCLK acts as the serial clock, and pin CS
acts as the serial chip select.
Each read/write operation is sequenced by the CS
signal and enabled by a LOW level to
to drive the chip with 2 bytes to 5 bytes, depending on the content of the instruction byte
(see Table 14
).
[1] R/W indicates whether a read (logic 1) or write (logic 0) transfer occurs after the instruction byte.
[1] Bits W1 and W0 indicate the number of bytes transferred after the instruction byte.
Bits A12 to A0 indicate the address of the register being accessed. In the case of a
multiple byte transfer, this address is the first register to be accessed. An address counter
is incremented to access subsequent addresses.
+0.9970703 111 1111 1100 011 1111 1100 0
+0.9980469 111 1111 1101 011 1111 1101 0
+0.9990234 111 1111 1110 011 1111 1110 0
+1.0000000 111 1111 1111 011 1111 1111 0
> [phone] 1111 1111 1
Table 13. Output codes
V
INP
− V
INM
Offset binary Two’s complement OTR pin
Table 14. SPI instruction bytes
MSB LSB
Bit 76543210
Description R/W
[1]
W1 W0 A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
Table 15. Read or Write mode access description
R/W
[1]
Description
0 Write mode operation
1 Read mode operation
Table 16. Number of bytes to be transferred
W1 W0 Number of bytes transferred
001 byte
012 bytes
103 bytes
1 1 4 or more bytes