Datasheet

ADC1113D125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 3 — 10 February 2011 21 of 41
NXP Semiconductors
ADC1113D125
Dual 11-bit ADC; serial JESD204A interface
11.5.2 ADC core output codes versus input voltage
Table 13 shows the data output codes for a given analog input voltage.
Fig 22. Detailed view of the JESD204A serializer with debug functionality
N
&
CS
N
&
CS
00
SCR
SCR
PRBS
8-bit/
10-bit
01
00
01
00
01
10
11
8-bit/
10-bit
PRBS
'0'
'0/1'
PRBS
'0'
'0/1'
PRBS
8
8
N + CS
N + CS
11 + 111 + 1
11 + 1
ADC A
PLL
AND
DLL
frame CLK
character CLK
bit CLK
10
10
11
10
01
00
SER
SER
11
10
00
11
10
00
× 1
× F
× 10F
DUMMY
ADC_PD
ADC_PD
ADC B
PRBS
FSM
(frame assembly
character
replication
ILA
test mode)
FRAME
ASSEMBLY
005aaa167
sync_request
11 + 1
bypass alignment
disable_char_repl
ADC_MODE[1:0]
SCR_IN_MODE[1:0]
SCR_IN_MODE[1:0]
LANE_MODE[1:0]
SWING_SEL[2:0]
LANE_POL
LANE_MODE[1:0]
LANE_POL
11 + 1
11 + 1
DUMMY
PRBS
ADC_MODE[1:0]
Table 13. Output codes
V
INP
− V
INM
Offset binary Two’s complement OTR pin
< −1 000 0000 0000 100 0000 0000 1
−1.0000000 000 0000 0000 100 0000 0000 0
−0.9990234 000 0000 0001 100 0000 0001 0
−0.9980469 000 0000 0010 100 0000 0010 0
−0.9970703 000 0000 0011 100 0000 0011 0
−0.996093 000 0000 0100 100 0000 0100 0
.... .... .... 0
−0.0019531 011 1111 1110 111 1111 1110 0
−0.0009766 011 1111 1111 111 1111 1111 0
0.0000000 100 0000 0000 000 0000 0000 0
+0.0009766 100 0000 0001 000 0000 0001 0
+0.0019531 100 0000 0010 000 0000 0010 0
.... .... .... 0
+0.9960938 111 1111 1011 011 1111 1011 0